Recently, devices adopting a multicore processor system configuration in which a single system has multiple cores are increasing. In a multicore processor system, the cores operate simultaneously, and therefore, have the potential of accessing the same device. When access contention occurs with respect to a device, an arbitration method by hardware or by software is performed in the multicore processor system.
An arbitration method by hardware, for example, is a method that uses an arbitration circuit. The arbitration circuit, for example, is disposed at the input/output port of the memory, which is one of the devices, and arbitrates access of the memory by the cores. In the arbitration method by hardware, the hardware performs the arbitration irrespective of software executed by a core not particularly performing any arbitration. For example, after a given core has acquired the access right to a device subject to arbitration, if the hardware that performs the arbitration receives from another core, an access request for the device, the hardware causes other core to wait until the given core has completed access and released the access right.
An arbitration method by software, for example, uses an exclusive access control function provided by an operating system (OS) of the multicore processor system and the software performs arbitration such that one core at a time accesses a device subject to arbitration. An arbitration method by software is applied, for example, when multiple cores access the same area of memory, or when a peripheral device such as a direct memory access controller (DMAC) or an image device such as a display are simultaneously accessed by multiple cores.
Nonetheless, irrespective of whether the arbitration method by hardware or software is performed, a core that has not obtained the access right has to wait until the access right is released and therefore, the processing performance of multicore processor system drops. Consequently, technology that circumvents access contention and prevents drops in processing performance have been disclosed.
For example, as an arbitration method by hardware, a technique has been disclosed that by OS scheduling, schedules processes that frequently access memory to not be executed simultaneously. Further, as an arbitration method by software, a technique has been disclosed that with respect to processes executed in parallel, even if acquisition of the access right fails, state transitions are regarded as executable states and are not put on standby, whereby the number of state transitions is reduced and the overhead accompanying state transitions is reduced (see, for example, Japanese Laid-Open Patent Publication Nos. 2000-148712 and H6-161872).
Recently, dynamic voltage and frequency scaling (DVFS) technology has been disclosed that varies clock frequency and voltage to realize reduced power consumption. DVFS separates the multicore processor system into units called power domains and varies the clock frequency and voltage according to domain. Use of DVFS enables the clock frequency and voltage of cores having a low load to be reduced to effect lower power consumption, or the clock frequency and voltage of cores having a high load to be increased to effect improved processing performance of the multicore processor system (see, for example, Japanese Laid-Open Patent Publication Nos. 2006-293768 and 2003-256069).
Nonetheless, among the technologies above, with the techniques according to Japanese Laid-Open Patent Publication Nos. 2000-148712 and H6-161872, neither contention nor overhead can be reduced and thus, a problem arises in that drops in performance occur. For example, among executable processes, if all the processes are processes that frequently access memory, irrespective of the scheduling that the multicore processor system performs, access contention occurs and processing performance decreases. Further, with the techniques according to Japanese Laid-Open Patent Publication Nos. 2006-293768 and 2003-256069, if DVFS technology is applied when contention occurs, a problem arises in that only two options are available, decrease the processing ability of an area having a low load or increase the processing ability of an area having a high load.